1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, relates to a semiconductor device with a test circuit, and a test method of the semiconductor device.
2. Description of the Related Art
In recent years, a data transfer rate between semiconductor devices has been increased, and transmission at a high data rate of, for example, several Gbps (Gigabit per second) is realized. In general, serial transmission is used for high-speed transmission rather than parallel transmission, since skew adjustment between signals is difficult in the parallel transmission. Additionally, it is necessary to process reception data in parallel inside the semiconductor device. Therefore, a signal transmitting and receiving circuit is provided with a circuit that carries out serial-parallel conversion (to be referred to as “SerDes circuit”, hereinafter). Such a SerDes circuit is provided with a serializer for converting a parallel data into a serial data, and a deserializer for converting the serial data into the parallel data.
The increase in the data transfer rate means that transmission and reception of a data signal can be carried out by using a clock signal with a higher frequency. At this time, degradation of the signal waveform of the data signal in the course of the transmission cannot be sometimes ignored. Therefore, it is necessary to previously test whether or not the SerDes circuit operates correctly even if the data signal with signal waveform degraded is supplied. For this purpose, the SerDes circuit is generally provided with a test signal generating circuit that outputs a test signal for testing a normal operation of the SerDes circuit. The test signal generating circuit conducts the test by receiving a test data signal transmitted from a transmitting circuit of the SerDes circuit and returning the test data signal to a receiving circuit without giving any change at all to the test data, as described in Japanese Laid Open Patent Application (JP-P2002-368827A). The SerDes circuit compares the test data signal outputted from the transmitting circuit and the returned test data signal, and determines whether a target circuit operates correctly.
FIG. 1 is a circuit diagram showing a configuration of a conventional test signal generating circuit 100. As shown in FIG. 1, the conventional test signal generating circuit 100 includes a differential amplifier circuit 101 having a first output node N201 and a second output node N202; a first capacitance 102; and a second capacitance 103. The first capacitance 102 is connected between a ground line VSS and the first output node N201. Similarly, the second capacitance 103 is connected between the ground line VSS and the second output node N202. The differential amplifier circuit 101 includes a differential transistor pair of a first transistor M201 and a second transistor M202; a constant current source M203 connected between the differential transistor pair and the ground line VSS; a first resistance R201; and a second resistance R202. The first resistance is connected between a power supply line VDD and the first node N201, and the second resistance R202 is connected between the power supply line VDD and the second output node N202.
With reference to FIG. 1, the test signal generating circuit 100 has a low-pass filter (an integrator circuit) of the first resistance R201 and the first capacitance 102, and a low-pass filter (integrator circuit) of the second resistance R202 and the second capacitance 103. Thus, the test signal generating circuit 100 receives, as a test signal, a first differential input Dmain+ supplied to the first transistor M201 and a second differential input Dmain− supplied to the second transistor M202 and outputs a first output signal Dout− and a second output signal Dout+.
In the conventional test signal generating circuit 100 shown in FIG. 1, the waveform of the test signal is degraded due to the low-pass filters or the integrator circuits. Thus, the test is accomplished to deal with a case where the waveform of a signal supplied from the outside of a chip is degraded. In this case, a waveform degradation rate at a frequency is determined based on the resistance and the capacitance in the low-pass filter (integrator circuit). However, there is a case where an actual signal waveform is not degraded in a constant rate. Thus, a technique is demanded that can carry out the test by optionally changing the signal waveform of the test signal.
Also, the resistance and the capacitance are independently affected by process variations. Therefore, the waveform degradation rate of the low-pass filter (integrator circuit) is also affected by the process variations. Consequently, the conventional test signal generating circuit 100 may generate a degradation signal different from a desired degradation signal. Thus, a technique is demanded that forms a test signal generating circuit less subject to the effect of the process variations in manufacturing the circuit.